orderin g numbe r : ena1609 bi-cmos ic for camera modules composite channel lens driver LV8483CS overview LV8483CS is a constant current driver ic for voice coil motors (vcm) that include s a constant current 1.5-channel driver. it uses an ultraminiature wafer level p ackage (wlp), which makes the ic ideal for vcm motor, shutter (sh), and iris (ir) drivers used in a wide variety of portab le equipment including camera cell phones. functions ? constant current driver for af vcm + constant current 1.5-channel h-bridge driver for sh and ir ? i 2 c bus interface ? l ow power consumption achieved using mos process technologies ? bu ilt-in 4-bit dac for constant current operatio n (used for sh and ir h-bridges) ? built-in 10-bit dac for constant curre nt co ntrol (used for af vcm driver) ? bu ilt-in constant current detection resistance ? w afer level packag e. wlp10 (0.97mm 2.47mm 0.5mmt) ? bu ilt-in thermal shutdown circuit and lvs circuit. ? a f vcm overshoot prevention function (current slope function) ? bu ilt-in sh/ir control pin (energization timing control function using trigger input) specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage v cc max 5.0 v output applied voltage v out max out1, out2, out3, out4 5.0 v input applied voltage v in max ena, scl , sda, sh/irtr -0.3 to +5.0 v gnd pin flow-out current ignd per channel 400 ma allowable power dissipation pd max with specified substrate * 550 mw operating temperature topr -30 to +85 c storage temperature tstg -40 to +150 c * specified substrate : 50mm 50mm 1.6mm, glass epoxy 2-layer board specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. 31710 sy pc 20091013-s00004 no.a1609-1/9
LV8483CS no.a1609-2/9 allowable operating conditions at ta = 25 c parameter symbol conditions ratings unit supply voltage v cc 2.5 to 4.5 v high level input voltage v ih 0.4 v cc to v low level input voltage v il ena, scl, sda and sh/irtr to v cc 0.13 v electrical characteristics at ta = 25c, v cc = 2.8v ratings parameter symbol conditions min typ max unit i cco ena = l 1 a supply current i cco 1 ena = h 0.7 1 ma pin input current 1 i in 1 ena, scl, sda 1 a pin input current 2 i in 2 sh/ir tr 28 a v cc low-voltage cutoff voltage vthv cc 2.0 v thermal shutdown temperature tsd design target value 175 c thermal hysteresis width tsd design target value 35 c output on resistance 1 (out1 + sencer) ron11 v cc = 2.8v, i out = 80ma (n-channel on-resistance + internal sensing resistor) 2.0 2.55 ron21 v cc = 2.8v, i out = 80ma (upper side + lower side + internal sensing resistor) 2.4 2.95 output on resistance 2 (out2 to out4 + sencer) ron22 v cc = 4.5v, i out = 100ma (upper side + lower side + internal sensing resistor) 2.0 2.4 af dac block resolution 10 bit relative accuracy inl 4 lsb differential linearity dnl 1 lsb full code current ifull 100 ma error code current 0 izero 1 a h bridge driver block output constant current dac1 i out 1 d3-d0code : 0000 260 ma output constant current dac9 i out 9 d3-d0code : 1000 180 ma output constant current dac16 i out 16 d3-d0code : 1111 110 ma energization time tsh d5-d4code : 00 10 ms output turn on time traise out2-out4 1 3 s output turn off time tfall out2-out4 0.2 1 s sda pin low level output v ol i o = 300 a 0.2 0.3 v * design guarantee value and no measurement is made.
LV8483CS package dimensions unit : mm (typ) 3362 pd max -- ta 0 0.6 0.55 0.29 0.4 0.2 0.8 ? 30 ? 20 75 20 40 60 80 0 100 ambient temperature, ta -- c allowable power dissipation, pd max -- w sanyo : wlp10(2.47x0.97) 2.47 0.97 0.5 max 0.14 top view side view side view bottom view 0.5 0.235 12345 0.5 0.235 0.27 pin assignment top view sh/ir tr out4 a b v cc out3 ena gnd sda out2 scl 12345 out1 no.a1609-3/9
LV8483CS block diagram ena sh/ir tr out2 out3 out4 v cc af vcm sh ir out1 0.5 scl sda 0.5 gnd + - + - i 2 c i/f control i 2 c dec 10bit dac vref lvs tsd 4bit dac current slope timing no.a1609-4/9
LV8483CS serial bus communication specifications i 2 c serial transfer timing conditions standard mode ton input waveform condition toff th1 ts1 ts2 th2 twh twl sda scl start condition stop condition ts3 tbus standard mode parameter symbol conditions min typ max unit scl clock frequency fscl scl clock frequency 0 100 khz ts1 setup time of scl with respect to the falling edge of sda 4.7 s ts2 setup time of sda with respect to the rising edge of scl 250 ns data setup time ts3 setup time of scl with respect to the rising edge of sda 4.0 s th1 hold time of scl with respect to the falling edge of sda 4.0 s data hold time th2 hold time of sda with respect to the falling edge of scl 0 s twl scl low period pulse width 4.7 s pulse width twh scl high period pulse width 4.0 s ton scl, sda rising time 1000 ns input waveform conditions toff scl, sda falling time 300 ns bus free time tbus interval between stop condition and start condition 4.7 s high-speed mode parameter symbol conditions min typ max unit scl clock frequency fscl scl clock frequency 0 400 khz ts1 setup time of scl with respect to the falling edge of sda 0.6 s ts2 setup time of sda with respect to the rising edge of scl 100 ns data setup time ts3 setup time of scl with respect to the rising edge of sda 0.6 s th1 hold time of scl with respect to the falling edge of sda 0.6 s data hold time th2 hold time of sda with respect to the falling edge of scl 0 s twl scl low period pulse width 1.3 s pulse width twh scl high period pulse width 0.6 s ton scl, sda (input) rising time 300 ns input waveform conditions toff scl, sda (input) falling time 300 ns bus free time tbus interval between stop condition and start condition 1.3 s no.a1609-5/9
LV8483CS i 2 c bus transmission method start and stop conditions the i 2 c bus requires that the state of sda be preserved while scl is high as shown in the timing diagram below during a data transfer operation. ts2 th2 scl sda when data is not being transferred, both scl and sda are in the high state. the start condition is generated and access is started when sda is changed from high to low while scl and sda are high. conversely, the stop condition is generated and access is e nded when sda is changed from low to high while scl is high. th1 th3 scl sda start condition stop condition data transfer and acknowledgement response after the start condition has been generated, the data is tr ansferred one byte (8 bits) at a time. generally, in an i 2 c bus, a unique 7-bit slave address is assigned to each device, and the firs t byte of the transfer data is allocated to the 7-bit slave address and to the command (r/w) indicating the transfer direction of the subsequent data. every time 8 bits of data for each byte are transferred, the ac k signal is sent from the receiving end to the sending end. immediately after the clock pulse of scl bit 8 in the data transferred has fallen to low, sda at the sending end is released, and sda is set to low at the receiving en d, causing the ack signal to be sent. when, after the receiving end has sent the ack signal, the tran sfer of the next byte remain s in the receiving status, the receiving end releases sda at the fa lling edge of the ninth scl clock. m s b l s b a c k l s b a c k m s b m s b l s b a c k w s7 scl sda 2nd byte start stop s6 s5 s4 s3 s2 s1 0 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 data data slave address 3rd byte 1st byte number of slave address is 0110011. (s7 s1) no.a1609-6/9
LV8483CS data transfer write format the slave address and write command must be allocated to the first byte and the re gister address in the serial map must be designated in the second byte. for the third byte, data transfer is carried out to the addr ess designated by the register address which is written in the second byte. subsequently, if data continues, the register address value is automatically incremented for the fourth and subsequent bytes. (*) thus, continuous data transfer starting at th e designated address is made possible. since no auto incrementing occurs for ad dress 02h and higher, it is necessary to send a stop condition after sending the data at address 02h. (*) since 2-byte data is allocated to address 00h, when resist er address 00h is specified in the second byte, the register address is auto-incremented to 01h after 2 bytes of data is sent. data write example data 3 0s start condition s stop condition p ack signal a master side transmission slave side transmission 1 10 01 1a 00 00 00 00 0a a data 2 3rd byte 2nd byte 1st byte data 1 aa p a 6th byte 5th byte 4th byte write data to address 00h (high byte) register address set to 00h slave address r/w = 0 written write data to address 02h write data to address 01h write data to address 00h (low byte) data 4 no.a1609-7/9
LV8483CS h-bridge energization timing charts energization time : internal setting mode ? ? ? energization is automatically stopped when the time that is selected from 10ms, 13ms, and 20ms expires. no.a1609-8/9 energization starts on a rising edge of the sh /ir tr signal in the external trigger mode. in the serial mode, energization is started by setting energization on with serial data. energization time : free mode ? ? ? starting and stopping of energization must both be set using the external trigger or serial data. in the external trigger mode, energization is started on a rising edge of the sh/ir tr signal and stopped on the falling edge. external trigger mode i out sh/ir tr serial mode energization "on" data transmit i out sda external trigger mode i out sh/ir tr serial mode energization "on" data transmit energization "off" data transmit i out sda in the serial mode, energization is started by setting en ergization on with serial data and stopped by setting it off.
LV8483CS sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. this catalog provides information as of march, 2010. specifications and information herein are subject to change without notice. ps no.a1609-9/9
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